unsigned 8-bit integer), which is used at line 7 and defined in ‘alt_types.h’ at Line 3. Lastly, ‘alt_u8’ is the custom data-type (i.e. ‘LED_BASE’ contains the based address, which is defined in ‘system.h’ file at Line 4 (see Fig. base, offset and data which are set to ‘LED_BASE’, ‘0’ and ‘led_pattern’ respectively at Line 15. IOWR(base, offset, data) at Line 15 is define in it. The ‘io.h’ file at Line 2, contains various functions for operations on input/output ports e.g.
NIOS MODELSIM SOFTWARE
In next section, Nios software will be used to create the blinking-LED system using ‘nios_blinkingLED.sopcinfo’ file.
In this way, SoPC system can be generated. Lastly, ‘ nios_blinkingLED_tb.spd’ is generated which is used by Nios software to start the simulation process. LEDs will be connected to FPGA board using this file whereas ‘ nios_blinkingLED_tb.qsys’ contains the information about simulation waveforms for the testbenches. The ‘nios_blinkingLED.qip’ file will be used for the creating the top module for the design i.e. ‘nios_blinkingLED.qip’ file) and simulation (e.g. 12.13, and contains various information about synthesis (e.g. These folders are generated as we select the ‘synthesis’ and ‘simulation’ options in Fig. Further, two more folders will be created inside the ‘nios_blinkingLED’ folder i.e. This file contains all the information about the components along with their base addresses etc. After this process, a ‘nios_blinkingLED.sopcinfo’ file will be generated, which is used by Nios-II software to create the embedded design. Next, rename the processor to ‘nios_blinkingLED’ and connect the clock and reset port to ‘clk’ device, by clicking on the circles as shown in Fig. Note that various errors are displayed in the figure, which will be removed in later part of this section. In component library, search for Nios processor as shown in Fig. Note that, renaming steps are optional but assigning appropriate names to the components is good practice as we need to identify these components in later tutorial. Rename ‘clk_0’ to ‘clk’ by right clicking the name (optional step). Next, follow the below steps to create the SoPC system, To open the Qsys tool, go to Tools–>Qsys in Quartus software. Since Qsys is the recommended tool by the Altera, therefore we will use this tool for generating the SoPC system. SoPC can be created using two tools in Quartus software i.e. It is recommended to read first two chapters before practicing the codes, as various issues related to the use of Nios software are discussed in these chapters.ġ2.4. Further, the outputs of this system is verified using Modelsim. In this chapter, these steps are discussed and a system is designed which displays the message on the computer and blinks one LED using FPGA board. 12.1, various steps are shown to design the SoPC system on the FPGA board using Nios-II processor. Nios II is a 32-bit embedded-processor architecture designed for Altera-FPGA board. we can design the embedded systems using Verilog/VHDL codes and implement them on the FPGA board. Further, SoPC systems are the programmable embedded systems i.e. Since, embedded systems are designed for specific tasks, therefore the designs can be optimized based on the applications. The Embedded systems are cost effective solution for such cases, where only few functionalities are required in the system. timers settings, displays and buzzers in microwave-ovens or washing machines etc., is not a cost effective choice. Selection of these computer systems for few specific applications, e.g. 
personal computers (PCs), support various end user applications. Before beginning the SoPC design, let’s understand the difference between ‘computer system’, ‘embedded system’ and ‘SoPC system’. In this tutorial, we will learn to design embedded system on FPGA board using Nios-II processor, which is often known as ‘System on Programmable chip (SoPC)’. Load the Quartus design (i.e.sof/.pof file) Modify BSP (required for using onchip memory)
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